(Not Applicable)
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit and a carrier which allows multiple chip packages to be quickly, easily and inexpensively mechanically registered and interconnected or assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the xe2x80x9cfootprintxe2x80x9d typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant""s U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits and carriers. The inclusion of the carriers in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significantly greater ease in achieving and maintaining the registry or alignment between the chip packages within the stack. Additionally, the use of the carriers significantly simplifies the interconnection or assembly of the chip packages into a chip stack.
In accordance with the present invention, there is provided a stackable integrated circuit chip package which comprises a carrier and a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the flex circuit is a conductive pattern. Also included in the chip package is an integrated circuit chip which is electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the carrier such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package.
In the chip package of the present invention, the carrier is sized and configured to be releasably attachable to the carrier of at least one other identically configured stackable integrated circuit chip package in a manner wherein the chip packages, when attached to each other, are maintained in registry along first and second axes which are generally co-planar and extend in generally perpendicular relation to each other. The carrier of the chip package has a generally rectangular top section which defines inner and outer surfaces and opposed pairs of longitudinal and lateral sides. In addition to the top section, the carrier includes a pair of identically configured side rail sections which extend along respective ones of the lateral sides of the top section. In the chip package, the substrate is wrapped about the carrier such that the first portion of the conductive pattern extends over a portion of the integrated circuit chip and the second portion of the conductive pattern extends over a portion of the outer surface of the top section. More particularly, the substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. In addition to being disposed upon a portion of the top surface of the substrate, the conductive pattern extends along the bottom surface of the substrate. The substrate is wrapped about the longitudinal sides of the top section of the carrier, and is sized relative to the carrier and the integrated circuit chip such that the lateral peripheral edge segments of the substrate extend along the outer surface of the top section in direct contact with each other.
The integrated circuit chip of the chip package of the present invention may be either a flip chip device or a BGA (ball grid array) device comprising a body having opposed, generally planar top and bottom surfaces. In addition to the body, the integrated circuit chip includes a plurality of conductive contacts which are disposed on the bottom surface of the body. The conductive contacts of the integrated circuit chip are electrically connected to the conductive pattern, and more particularly to that portion of the conductive pattern disposed on the top surface of the substrate. The electrical connection of the conductive contacts of the integrated circuit chip to the conductive pattern is preferably accomplished through the use of a Z-axis pad disposed between the bottom surface of the body and the top surface of the substrate. The integrated circuit chip of the chip package may also be a TSOP (thin small outline package) device comprising a body having opposed, generally planar top and bottom surfaces, an opposed pair of longitudinal sides, and an opposed pair of lateral sides. In addition to the body, this particular integrated circuit chip includes a plurality of conductive leads which protrude or extend from each of the longitudinal sides of the body. The conductive leads of the integrated circuit chip are electrically connected to the conductive pattern of the substrate of the flex circuit via the Z-axis pad.
In the chip package of the present invention, the substrate is preferably attached to the carrier through the use of an acrylic film adhesive. As will be recognized, portions of the top surface of the substrate adjacent respective ones of the lateral peripheral edge segments thereof are secured to a portion of the outer surface of the top section of the carrier through the use of the aforementioned adhesive. The substrate itself is preferably fabricated from a polyamide having a thickness in the range of from about 1 mil to 8 mils. The carrier may be injection molded from a rigid plastic material, and more particularly polycarbonate, or may alternatively be fabricated from a sheet metal material.
To facilitate the releasable attachment of the carrier of the chip package to the carrier of another identically configured stackable integrated circuit chip package, the carrier is preferably formed to include four attachment tabs which are integrally connected to the top section of the carrier and protrude upwardly from the outer surface thereof. The attachment tabs are preferably arranged in two pairs which are disposed along respective ones of the longitudinal sides of the top section in opposed relation to each other. In addition to the attachment tabs, the carrier preferably includes a pair of alignment slots which are disposed within the top section adjacent respective ones of the lateral sides thereof. Also included on the carrier is a pair of alignment tabs which protrude from respective ones of the side rail sections thereof in aligned relation to respective ones of the alignment slots.
The attachment tabs are engageable (i.e., mechanically interlockable) to respective ones of the side rail sections of the carrier of another stackable integrated circuit chip package, with the alignment tabs being releasably insertable into respective ones of the alignment slots of the carrier of another stackable integrated circuit chip package. Additionally, the alignment slots are adapted to receive respective ones of the alignment tabs of the carrier of another stackable integrated circuit chip package. In this respect, the mechanical interlock of the attachment tabs of the carrier to the side rail sections of the carrier of a chip package stacked thereupon maintains the chip packages in registry along the first axis, and more particularly maintains the second section of the conductive pattern of the lower chip package in registry or alignment along the first axis with the first portion of the conductive pattern of the upper chip package stacked thereupon. Additionally, the insertion of the alignment tabs of the carrier of the upper chip package into respective ones of the alignment slots of the carrier of the lower chip package maintains the stacked chip packages in registry along the second axis, and more particularly maintains the second portion of the conductive pattern of the lower chip package in registry along the second axis with the first portion of the conductive pattern of the upper chip package in the chip stack.
The chip package of the present invention is preferably used in combination with a base chip package which is similar in structure to the above-described chip package. The sole distinction between the base chip package and the chip package lies in the structure of the base carrier of the base chip package which differs from the carrier of the chip package in relation to the configuration of the side rail sections thereof. More particularly, the side rail sections of the base carrier do not each include one of the above-described attachment tabs, but rather are each formed to include a flange portion which extends laterally outward from the remainder thereof. The flange portions of the side rails sections of the base carrier are attachable to a mother board, and function as heat sinks. The releasable attachment of a chip package to a base chip package is accomplished in the same manner described above in relation to the releasable attachment of any two chip packages to each other. In this respect, the attachment tabs of the base carrier of the base chip package are engaged or mechanically interlocked to respective ones of the side rail sections of the chip package stacked thereupon, with the attachment tabs of such chip package being inserted into respective ones of the alignment slots of the base carrier of the base chip package. Advantageously, thermally conductive contact is achieved between the chip package and the base chip package due to the abutment of the side rail sections of the chip package to the top section of the base carrier, with such thermally conductive contact also being achieved between interconnected chip packages within the chip stack attributable to the abutment of the side rail sections of the carrier of a chip package to the outer surface of the top section of the carrier of the chip package immediately therebelow. The chip stack of the present invention may be constructed using any number of chip packages interconnected or mechanically interlocked to each other and to a base chip package.